mipsel_mips32

Imagination’s MIPS32 architecture is a highly performance-efficient, industry standard architecture that is at the heart of billions of electronic products, from tiny microcontrollers to high-end networking equipment. It provides a robust instruction set, scalability from 32-bits to 64-bits, a broad-spectrum of software development tools and widespread support from numerous partners and licensees.

The MIPS32 architecture provides seamless upward compatibility to the 64-bit MIPS64® architecture, bringing powerful features, standardized privileged mode instructions, and support for past ISA versions. The MIPS32 architecture incorporates important functionality including SIMD (Single Instruction Multiple Data) and virtualization. These technologies, in conjunction with technologies such as multi-threading (MT), DSP extensions and EVA (Enhanced Virtual Addressing) enrich the architecture for use with modern software workloads which require larger memory sizes, increased computational horsepower and secure execution environments.

The MIPS32 architecture is based on a fixed-length, regularly encoded instruction set and uses a load/store data model. The architecture is streamlined to support optimized execution of high-level languages. Arithmetic and logic operations use a three-operand format, allowing compilers to optimize complex expressions formulation. Availability of 32 general-purpose registers enables compilers to further optimize code generation for performance by keeping frequently accessed data in registers.

A set of registers reflects the configuration of the caches, MMU, TLB, and other privileged features implemented in each core. By standardizing privileged mode and memory management and providing the information through the configuration registers, the MIPS32 architecture enables real-time operating systems, other development tools, and application code to be implemented once and reused with various members of both the MIPS32 and the MIPS64 processor families.

Flexibility of its high-performance caches and memory management schemes are strengths of the MIPS architecture. The MIPS32 architecture extends these advantages with well-defined cache control options. The size of the instruction and data caches can range from 256 bytes to 4 MB. The data cache can employ either a write-back or write-through policy. A no-cache option can also be specified. The memory management mechanism can employ either a TLB or a Block Address Translation (BAT) policy. With a TLB, the MIPS32 architecture meets Windows CE, Linux and Android memory management requirements.

source

Package architectureTargetSubtarget BrandModelVersion
mipsel_mips32au1000au15004G SystemsAccessCube (MeshCube)
mipsel_mips32ar7genericAVMFRITZ!Box Fon WLAN 7170
mipsel_mips32ar7ActiontecGT724WG
mipsel_mips32ar7ActiontecGT701C, D
mipsel_mips32ar7ActiontecGT704WG1A
mipsel_mips32brcm47xxlegacyAsusWL-320gP
mipsel_mips32brcm47xxlegacyAsusWL-330gE
mipsel_mips32brcm47xxlegacyAsusWL-500bv1
mipsel_mips32brcm47xxlegacyAsusWL-500g
mipsel_mips32brcm47xxAsusWL-500g Deluxe
mipsel_mips32brcm47xxlegacyAsusWL-500g Premiumv1
mipsel_mips32brcm47xxlegacyAsusWL-500g Premiumv2
mipsel_mips32brcm47xxlegacyAsusWL-500W
mipsel_mips32brcm47xxlegacyAsusWL-520gU
mipsel_mips32brcm47xxlegacyAsusWL-550gE
mipsel_mips32brcm47xxlegacyAsusWL-HDD2.5
mipsel_mips32brcm47xxlegacyBelkinF5D8230-4v1002
mipsel_mips32brcm47xxlegacyBuffaloBHR-4RV
mipsel_mips32ar7genericBuffaloWBMR-G54
mipsel_mips32brcm47xxlegacyBuffaloWHR-G125
mipsel_mips32brcm47xxlegacyBuffaloWZR-RS-G54
mipsel_mips32brcm47xxlegacyCatch TecCW5354U
mipsel_mips32brcm47xxlegacyD-LinkDIR-320A1
mipsel_mips32brcm47xxlegacyD-LinkDIR-330A1
mipsel_mips32ar7D-LinkDSL-502T Gen IIC5
mipsel_mips32ar7D-LinkDSL-504TC3
mipsel_mips32ar7genericD-LinkDSL-524TA1 (EU)
mipsel_mips32ar7D-LinkDSL-584TA1 (EU)
mipsel_mips32ar7genericD-LinkDSL-G624TA1 (EU)
mipsel_mips32ar7D-LinkDSL-G684TA1 (EU)
mipsel_mips32brcm47xxlegacyHuaweiE970
mipsel_mips32ar7LinksysAG241v1
mipsel_mips32ar7LinksysAG241v2
mipsel_mips32ar7LinksysAG241v2b
mipsel_mips32ar7LinksysRTP3001.0
mipsel_mips32ar7LinksysWAG54Gv2
mipsel_mips32ar7LinksysWAG54Gv3
mipsel_mips32ar7LinksysWAG200G
mipsel_mips32ar7LinksysWAG220Gv1
mipsel_mips32ar7LinksysWAG354G
mipsel_mips32ar7LinksysWAG354Gv2
mipsel_mips32brcm47xxlegacyLinksysWRH54G1.0
mipsel_mips32brcm47xxlegacyLinksysWRT54G2.0, 2.2, 3.0
mipsel_mips32brcm47xxlegacyLinksysWRT54G1.0
mipsel_mips32brcm47xxlegacyLinksysWRT54G1.1
mipsel_mips32brcm47xxlegacyLinksysWRT54G3.1
mipsel_mips32brcm47xxlegacyLinksysWRT54GS1.0, 1.1, 2.0
mipsel_mips32brcm47xxlegacyLinksysWRT150Nv1
mipsel_mips32brcm47xxgenericLinksysWRT600N1.1
mipsel_mips32ar7LinksysWRTP54G1.0
mipsel_mips32brcm47xxlegacyLinksysWRTSL54GS1.0, 1.1
mipsel_mips32adm8668genericLinksysWRTU54G-TM
mipsel_mips32brcm47xxgenericLinksysWRT310Nv1
mipsel_mips32brcm47xxgenericLinksysE30001.0
mipsel_mips32brcm47xxgenericLinksysWRT300N1.1
mipsel_mips32brcm47xxlegacyLinksysWRT300N1.0
mipsel_mips32brcm47xxgenericLinksysWRT350Nv1
mipsel_mips32brcm47xxgenericLinksysWRT610Nv1.0
mipsel_mips32brcm47xxgenericLinksysWRT610Nv2.0
mipsel_mips32rb532genericMikroTikRB532
mipsel_mips32rb532genericMikroTikRB532A
mipsel_mips32ar7NetgearDG834Gv1, v2
mipsel_mips32ar7NetgearDG834Gv3
mipsel_mips32brcm47xxlegacyNetgearWGT634U
mipsel_mips32brcm47xxlegacyNetgearWNR834Bv2
mipsel_mips32brcm47xxlegacyNetgearWNDR3300v1
mipsel_mips32brcm47xxlegacyOptionGlobesurfer III
mipsel_mips32ar7T-Com / TelekomSpeedport W 501V
mipsel_mips32ar7genericT-Com / TelekomSpeedport W 701V
mipsel_mips32ar7T-Com / TelekomSpeedport W 721V
mipsel_mips32ar7ZyXELP-2602HWN-D7A